The present invention relates to semiconductor memory devices, and more particularly, to nonvolatile semiconductor memory devices and methods of forming the same.
Nonvolatile memory devices may retain stored data even if the power supply is interrupted. The nonvolatile memory devices can be classified into NAND-type flash memory devices and NOR-type flash memory devices depending on a connection structure. In the NAND-type flash memory device, a string selection transistor SSL, a plurality of memory cell transistors and a ground selection transistor GSL may be connected in series. The string selection transistor may be connected to a bit line through a contact plug, and the ground selection transistor may be connected to a common source line CSL.
A programming procedure for the NAND-type flash memory device may include applying a voltage of 0V to a selected bit line, and applying a power supply voltage Vcc of 1.8V˜3.3V to a gate of the string selection transistor. Accordingly a channel voltage of a cell transistor connected to the selected bit line may be 0V. A program voltage Vpgm may be applied to a selected word line such that electrons may be injected into the selected cell transistor by Fowler-Nordheim (FN) tunneling. A self-boosting method may be used in order to prevent the cell transistor connected to a non-selected bit line and the selected word line from being programmed.
A conventional self-boosting method may include applying a voltage of 0V to a gate of the ground selection transistor to interrupt a ground path. The power supply voltage Vcc may be applied to the non-selected bit line and a gate of the non-selected string selection transistor as a program inhibition voltage. The program voltage Vpgm may be applied to the selected word line and a pass voltage Vpass may be applied to the non-selected word line. Therefore, the channel voltage of the non-selected cell transistor may be boosted and it may be possible to prevent the non-selected cell transistor from being programmed. However, in the conventional self-boosting method, a leakage current may be generated in junction regions between the string selection transistor and memory cell transistor adjacent thereto, and between the ground selection transistor and the memory cell transistor adjacent thereto. Moreover, a gate induced drain leakage current (GIDL) and/or a band-to-band tunneling (BTBT) may be generated in the junction regions. Therefore, the self-boosting level may be reduced.
Meanwhile, in a conventional NAND-type flash memory, a soft program may occur due to hot carriers when applying the program inhibition voltage. The soft program caused by the hot carriers may frequently occur in the memory cell transistor most adjacent to the ground selection transistor. When applying the program inhibition voltage, the power supply voltage Vcc may be applied to the gate of the string selection transistor, but the voltage of 0V may be applied to the gate of the ground selection transistor. The ground selection transistor may have a channel voltage that may be different from the boosting voltage. Thus, the program phenomenon due to the hot carriers may take place in a memory cell transistor immediately adjacent to the ground selection transistor. That is, the soft program may occur in the immediately adjacent memory cell transistor.